letzter Beitrag von everslick am
I am wondering why the MEGA65 will only have 8 cores in its "core selector"? Why is it limited to this? There is of course a reason, I understand that, but why isn't it possible to put in e.g. a 64GB SD card and select between all available (future) cores?
I am not sure I ever will use 8 cores anyhow, but if the MEGA65 gets a success, with a lot of different cores, then I assume 8 would be too small to have a dynamic selecting of choices? 
As far as I know, the cores are stored on the FPGA memory, not on the SD card.
Only the first time, when you flash a new core from the SD to the FPGA, you store the (new) core on the SD card.
But, you can store as many cores as you like on the SD card, and flash it to one of the 7 available cores when you like to use that core.
As far as I know, the cores are stored on the FPGA memory, not on the SD card.
Only the first time, when you flash a new core from the SD to the FPGA, you store the (new) core on the SD card.
But, you can store as many cores as you like on the SD card, and flash it to one of the 7 available cores when you like to use that core.
But why store the 8 cores in the FPGA and not take it directly from SD when needed? I know too little of this, but I would expect that you would need to reprogram the FPGA every time you need a new core and you could have an even bigger core, if you didn't already have 7 other cores in it?
Sorry, but I still don't understand it and why it is needed to have 8 cores available in the FPGA 
Is it because it takes less time to reprogram, when it already is in FPGA or .. ?
Loading a bitstream from internal FPGA memory (not sure how that partition is called) is much faster than loading from SD. Boot speed is roughly the same speed as a traditional hardware solution.
Everytime when you do a cold start, the FPGA needs to be programmed, that process is much faster when the core is already “available” on the FPGA.
The FPGA loads the core from an SPI-FLASH chip, not from SD-Card. This SPI-Flash chip has 8 slots for cores. The attached image shows the ways the bitstream can take. Pls ask, if there are still questions left.
