As promised ttlworks and I also dissected the 6509R7...
as before Dieter M. aka ttlworks wrote the documentation and I just copied it from his
"home forum" to Forum64... this implies that although I posted the pictures here the
majority of work is his!
Enjoy this great (IMHO) piece of documentation!!!
//Previous thread: 8501 dissected : Some parts of the 8501 and 6509 chip layout do look very similar, some other parts don't.
This thread is about a transistor level dissection of what makes the 6509 different from the 6502,
brought to you by Frank Wolf and ttlworks.
The 6509 was used in the ill-fated Commodore CBM-II line of computers (released 1982, discontinued 1984).
It was capable of addressing 1MB of RAM via bank switching (16 blocks of 64kB by a cumbersome sort of MMU), but had a reputation for being difficult to program, and never fared well.
In addition to A0..A15, it has four additional address pins, namely P0..P3.
There are two 4 Bit registers inside the chip, a RESET sets all of the register Bits.
Register 1 (located at $0001 in memory) is placed on P0..P3 when the CPU reads data from memory by using 'LDA (ind),y' or writes data to memory by using 'STA (ind),y'.
Else, register 0 (located at $0000 in memory) is placed on P0..P3.
Means, the first two Bytes ($0000 and $0001) of every 64kB block of memory can't be used, because the two MMU registers always are mapped there.
When reading these address locations, the CPU does a read cycle on the bus, but discards the data.
When writing these address locations, the CPU does a read cycle on the bus, but discards the data: R/W# is forced to 1, and the D0..D7 data bus drivers are disabled.
For consistence with Frank's notation, low_active signals are named foo#, not /foo.
For the cheat sheet, I decided to stick with the 8501 workflow, because it was economical to use copy&paste when writing text about parts where the chip designers had used copy&paste,
and that's why the 8501 topics 1) and 3) are missing in the 6509 cheat sheet: 6509 has no bias generator, and no GATE_IN logic.
Orientation for all the chip pictures: PHI1(in) is North.