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STZ on 65C02 and 65CE02

  • Just an info about using STZ on C65/MEGA65 (65CE02 CPU):


    If you use a code written for the 65C02 on the C65/MEGA65 it is important to know this difference:


    On the 65C02 STZ (opcode $64,$74,$9C, $9E) means "Stores a zero byte value into memory":


    (Source: http://www.obelisk.me.uk/65C02/reference.html)


    On the 65CE02 STZ (also the same opcodes $64,$74,$9C, $9E) means "Store Z register to memory":


    Be aware of the typo in this table (it has to be correctly 65CE02) :S:


    (Source: https://www.commodore.ca/manua…ments/chipdata/65ce02.txt)


    It means that STZ on the 65C02 always stores zero into the memory and on the 65CE02 the exact same command with the exact same opcodes stores the value of the z register into the memory!


    If Z was set to 0, STZ behaves the same on the 65CE02 as on the 65C02. :zeig:


    Knowing and remember this can save you days of debugging while trying to use a 65C02 code an the C65/MEGA65! I know what I'm talking about! :bgdev

  • If Z was set to 0, STZ behaves the same on the 65CE02 as on the 65C02.

    Which document about the 65ce02 have you been reading? Which one does not explain this?! :D


    If this was news to you, you might want to take a closer look at the opcodes 12, 32, 52, 72, 92, b2, d2 and f2: On the 65c02, they use indirect addressing. On the 65ce02, they use indirect-z-indexed addressing. The reasoning is the same: If Z is zero, it does not make a difference (and therefore is backward-compatible), but having an additional register is much more useful than the old functionality.

  • If Z was set to 0, STZ behaves the same on the 65CE02 as on the 65C02.

    Which document about the 65ce02 have you been reading? Which one does not explain this?! :D

    This one: https://www.commodore.ca/manua…ments/chipdata/65ce02.txt :)


    Having read a document and remembering exact that issue if you have a complete other error source in mind are two different things. :D

  • It means that STZ on the 65C02 always stores zero into the memory and on the 65CE02 the exact same command with the exact same opcodes stores the value of the z register into the memory!


    If Z was set to 0, STZ behaves the same on the 65CE02 as on the 65C02. :zeig:


    Knowing and remember this can save you days of debugging while trying to use a 65C02 code an the C65/MEGA65! I know what I'm talking about! :bgdev

    Yes, that was the intent, to extend/enhance 65C02 (thus maybe the "E" in "CE" ... compared to "C") to be compatible. That is, while Z register is zero and not touched, it's totally compatible with 65C02 in this topic. Also, addressing mode of 65C02 (ZP) (without any index register involved) was changed to (ZP),Z in 65CE02. Again, while register Z is zero, it's the very same thing, compatible, but you can opt in using Z as a "true" index register on 65CE02. In my opinion is quite clever, to re-use existing opcode to offer more, but still providing compatibility as well. Btw, STZ also exists on 65816, the same story it simply means "store zero" there.

  • Actually, I would prefer .Z register to stay 0 all the time, it causes portability problems as described above. One of the reasons I've decided not to reuse Commander X16 DOS after all.

    Actually, I'm tempted to use TBA as a replacement of LDA #$00 in the ROM, but I'm a little bit scared :)

  • Actually, I would prefer .Z register to stay 0 all the time, it causes portability problems as described above. One of the reasons I've decided not to reuse Commander X16 DOS after all.

    Actually, I'm tempted to use TBA as a replacement of LDA #$00 in the ROM, but I'm a little bit scared :)

    But then you lose the power of another index register. Also MEGA65 uses Z register, eg with the "32 (well 28 ...) bit linear addressing mode" (yes, you can modify the 4 byte long ZP pointer but if need to "travel" few bytes relative to ZP, much faster to say INZ ...), and also the "Q" opcodes, when AXYZ forms one 32 bit register, so anyway Z will be modified. But surely, if you mean about portability in a way that you won't use MEGA65 features anyway at all, these are not legit reasons as on 65C02 STZ stores zero for example, end of story.

  • Also MEGA65 uses Z register

    Yes, that's a great advantage. But the code will run (nearly) only on the MEGA65 (C65). The 65CE02 is so rare that nearly no other item use it. A 6502 or even 65C02 code will run on much, much more items.


    Developing code for the MEGA65 is for a very, very little user base. At least as long as the 1.000.000 item of the MEGA65 will be sold. ;)

  • Till now I haven' used the .Q register a single time as of yet, and .Z is of limited use - not many addressing modes use it. Honestly, I would prefer to have LDA [...], Y, but not limited to zero page for the pointer, and a more efficient MAP, not trashing every single register.


    But that's me, my use cases are rather specific :)