Beiträge von ivettaB im Thema „Wie 6510 vom Expansionsport aus "anhalten"?“

    Zitat
    Ready (RDY) - This input signal allows the user to single cycle the microprocessor on all cycles except write cycles. A negative transition to the low state during or coincident with phase one (01) and up to 100ns after phase two (02) will halt the microprocessor with the output address lines reflecting the current address being fetched. This condition will remain through a subsequent phase two in which the Ready signal is low. This feature allows microprocessor interfacing with low speed PROMS as well as fast (max. 2 cycle) Direct Memory Access (DMA). If Ready is low during a write cycle, it is ignored until the following read operation.

    So, besides what is specified for timing in the question, the critical bit is that you need to wait until a read cycle is being setup by the CPU.

    In the case of the REU, this is implicit in how the device works. Since the DMA operation is triggered by the CPU writing to the I/O space ($DE00), the following CPU operation would be to fetch the next instruction. So that guarantees a read is being setup by the CPU when the REU asserts D̅M̅A̅ during Phi2 low.

    To summarize, D̅M̅A̅ should be asserted while Phi2 is low and BA is high, AND with the CPU pending a READ operation. Then, the DMA device (REU) is able to master the bus on the next Phi2 high cycle, and may continue to do so unless BA is removed. In that case, it has to wait on the VIC-II to reassert BA, and then continue. When the operation is done, the D̅M̅A̅ signal is removed by the device, and then the CPU continues with its read operation.

    Der DRAM Refresh vom VIC läuft ja normal bei PHI2=L aber du hast ja den BUS übernommen. Inwieweit sich das auf Deine Applikation auswirkt müsste man mit Logic Analyzer ausmessen. BA=L wird ja nur bei Badlines gemacht und da wird aber keine Refreshadresse generiert soweit ich mich noch erinnere.