Actually that's not a property of NMOS. You can implement dynamic and static logic in NMOS and in CMOS. And it's still used today, since it saves real estate. Just think of DRAM.
This is an example in CMOS:
Bitte melde dich an, um dieses Bild zu sehen.
In NMOS it's done slightly different. The bit is stored in the capacity of the totem pole FETs here when Phi is low. It is fed whenever Phi is high. This is also the reason for what you saw: As long as Phi is high (or low, depending from the implementation), you can change D_in. It is stored when the input FET is switched off. Often you have cascades of these dynamic latches, first gated with Phi2 and the second with Phi1. Phi1 is created internally and is a non-overlapping, inverse clock.
This is by the way the reason that the datasheets not only state a maximal clock rate but also a minimal. Your screenshot merlintwa shows that you are way below it (if the time axis is correct), but it seems there is enough margin in the design. Nice that you have VCD now ![]()