After that work I found I can now reproduce anything the CIA reports back on the Timer A output when in CNT count mode, using this input circuit: CNT is an input to a normal D-type Flip-Flop with an Asynchronous reset input. This feeds another flipflop that synchronizes the detected posedge to the PHi2 clock domain, and its output also resets the edge detector. So during the actual internal count pulse (when cnt_rr=1), you can do whatever you want on the CNT input - it is ignored.
The Verilog you posted suggests that the second flip flop is clocked from the negative PHI2 edge, which matches exactly what I observed, doesn't it? The time between the positive CNT edge and the times that I marked "1" is the period between the two events. The difference between the Timer A logic you describe and the SR logic would be that the latter takes one PHI2 cycle longer.
The funny thing is, the duty cycle issue you mention doesn't seem to come up in my tests for timer A. The rising edge is detected regardless if it is just a very short 1->0->1 pulse (like in your graph) or if it is a very short 0->1->0 pulse, or of it already goes 1->0 in the cycle before the posedge. Maybe it is a Serial Register exclusive issue, to do with that trasparent path I found. I will research that.
I think that's a misunderstanding. You're probably referring to what I wrote in Bitte melde dich an, um diesen Link zu sehen.? Maybe "duty cycle" was bad wording. I was talking about the behaviour of the 6526 when sending. It sets CNT low at the beginning of a bit cycle and then does one low -> high transition at 50% of the bit cycle and keeps CNT high for the rest of the bit cycle. What I meant is that this transition has to be earlier than the 50% mark of the bit cycle because in the worst case it can take ~2,5 PHI2 cycles from the positive edge of CNT until SP is sampled (as outlined in Bitte melde dich an, um diesen Link zu sehen.) while 50% of the bit cycle is only 2,0x PHI2 at the highest data rate.
That does *not* mean, that something like this, with only a short positive CNT pulse, would not work:
|<- >2 phi2 cycles ->|
PHI2 |____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾
CNT ‾‾‾‾‾‾‾‾|__|‾‾|_____________________|‾‾‾‾‾‾‾‾‾‾‾‾‾
SP ‾‾‾‾‾‾‾‾|___________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾
^ ^
1 2
Is that what you meant? I never checked anything like that, I only experimented with having the CNT low -> high transition at different points in the bit cycle.
What I don't understand is the "... or of it already goes 1->0 in the cycle before the posedge" part. I guess "1->0" refers to CNT (?), but "posedge" of what? PHI2? Shouldn't this be "negedge" then? In that case I would agree (it's what my "diagram" above shows, right?).