What is the part of the work with these free tools you don't like?
......
Would you be interested in some SVG-to-other converer?
I cannot recall ATM which limitations I didn't like but some tools didn't work with .svg files and that's what I use in my workflow.
Most of the professional tools I tried have *much* more features than I really need for the rather simple MOS/CSG chips.
In fact I had to spend more time figuring out stuff like process parameters, W/L dimension settings
just to get some simple gates to be detected correctly.
Therefore I started programming a .svg to netlist converter (75% finished) which produces simple(!)* transistor netlists which
I can then feed into my netlist simulator (already working but not very configurable; 95% finished).
I also used some professional tools (which I rented due to the extremely high price) to convert
several Original MOS/CSG GDS-II files (e.g. MOS6522 or CIA-Variant CSG8520R4...) into netlists...
but I haven't fed the lists into my simulation yet. That means I don't know if they are correct (yet). 
The last tool I want to redo is something like the well known tools from Peter Monta.
In other words converting the netlists into either synthesizable or (in a first step) simulatable
Verilog code (due to the use of *really* bi-directional transmission gates).**
*No W/L extraction; just transistors+nodes to be used for switch-level simulation.
** The transmission gates are used bi-directionally. It's not always clear which side is source and which side is sink.
Therefore simulation would be the first step and if I lose motivation the last one. LOL