In my opinion the /CASRAM has to be connected directly to /CS1 for having a full timings during the READ acces,
indeed an original D-Ram during a READ cycle remain enabled until /CASRAM is enabled: a S-Ram read cycle can't be better if shortened, instead a too much short enabling could make problems to CPU reading timings...
Write cycle:
R/W has to be ORed with PH0 (pin 17 of the VICII) and connected to CS2 for limiting only the WRITE time to a point where the DATA and the ADDRESS is still stable: the S-Ram need stable DATA and ADDRESS during all the selection time in write cycle, D-Ram don't need it (the D-Ram will "sample" column and Data on falling edge of /CAS).
The different delays between 74LS257 from different manufacturer could explain why some write cycle could be corrupted, and some not.
If someone owner of "crashing" machines will try "/CS1=/CASram" and "CS2=(R/W # PH0)" my suspect will be resolved: or it become a well working machine, or not.
In positive case could be applied strategies that imply only signals from D-Ram sockets, but before it I need a test on "capricious" computers.