I can share the schematic if anyone is interested.
Thank you, please share the schematics. : emojiSmiley-106:
Here is a simplified schematic. It is missing 4 configuration resistors which select if neatSRAM is installed to a 2 or 8 DRAM chip motherboard.
CAS also got its own latch. RAS latch is latched when RAS signal goes down but it is released when both RAS and CAS are high (AND-gate U5).
SRAM output is controlled by CAS as with original DRAM.
I enabled pin swap to latch inputs and SRAM address and data pins. You can scramble address and data pins and the memory works the same. This made layout easier.