@Freddy Champagne: It has nothing to do with the C128.
In the C65, the 4510 was designed to handle a 1MB address space via bank switching: although it can access only 64K directly, but its two 32K segments can be mapped to anywhere within the 1MB individually (by the processor itself). The space contains both RAM and ROM which is 256K in the prototype machines (128K RAM + 128K ROM) and above which an optional 512K RAM expansion was planned.
The DMAgic is more capable than the REU and its address space also involves the system RAM (so the first 1MB is common). It can handle up to 8MB by design. (So thus it is more similar to the DMA controller in the C64DTV which has got 2MB built in that contains the first 64K, too.)
In the MEGA65, both the mapper and the DMAgic are further expanded by Paul to work even up to a 32-bit address space.