Hi,
the "Xilinx XC7A100T" has probably 101440 Logic Cells / 15850 Slices.
My question is how many of these Logic Cells / Slices are currently already used?
And how many are therefore still available for enhancements and new features?
Can I even know which part (VICTOR, BILL, SID, etc.) how many Logic Cells / Slices occupied (approximately)?
thanks and best regards
Hans
Currently the FPGA is about 70% full, which is as high as I want it to go with all the vital features. In practice, there are a few things that still need including, so I might have to do some optimising to make enough space.
I think the last time I looked:
CPU - 25-30%
VIC-IV - 25%
Serial debug interface - 5-10%
But these are only numbers I am pulling from the air from memory. We are doing quite a bit of work behind the scenes at the moment, so I will give some updated figures when they are available.
Paul.
I have just compiled the design from:
https://github.com/gardners/c65gs/tree/hyperinterruptdebug
and ISE reports the following:
in "Synthesis/DeviceUtilization":
```Device utilization summary:
---------------------------
Selected Device : 7a100tcsg324-1
Slice Logic Utilization:
Number of Slice Registers: 25033 out of 126800 19%
Number of Slice LUTs: 43631 out of 63400 68%
Number used as Logic: 38023 out of 63400 59%
Number used as Memory: 5608 out of 19000 29%
Number used as RAM: 5432
Number used as SRL: 176
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 49141
Number with an unused Flip Flop: 24108 out of 49141 49%
Number with an unused LUT: 5510 out of 49141 11%
Number of fully used LUT-FF pairs: 19523 out of 49141 39%
Number of unique control sets: 1327
IO Utilization:
Number of IOs: 175
Number of bonded IOBs: 172 out of 210 81%
IOB Flip Flops/Latches: 100
Specific Feature Utilization:
Number of Block RAM/FIFO: 122 out of 135 90%
Number using Block RAM only: 122
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number of DSP48E1s: 14 out of 240 5% ```
and in "PAR/DeviceUtilization":
```Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 25,003 out of 126,800 19%
Number used as Flip Flops: 24,963
Number used as Latches: 20
Number used as Latch-thrus: 0
Number used as AND/OR logics: 20
Number of Slice LUTs: 36,034 out of 63,400 56%
Number used as logic: 30,129 out of 63,400 47%
Number using O6 output only: 21,053
Number using O5 output only: 717
Number using O5 and O6: 8,359
Number used as ROM: 0
Number used as Memory: 5,212 out of 19,000 27%
Number used as Dual Port RAM: 2,972
Number using O6 output only: 2,456
Number using O5 output only: 36
Number using O5 and O6: 480
Number used as Single Port RAM: 2,066
Number using O6 output only: 2,050
Number using O5 output only: 0
Number using O5 and O6: 16
Number used as Shift Register: 174
Number using O6 output only: 172
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 693
Number with same-slice register load: 617
Number with same-slice carry load: 76
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 10,990 out of 15,850 69%
Number of LUT Flip Flop pairs used: 38,262
Number with an unused Flip Flop: 19,700 out of 38,262 51%
Number with an unused LUT: 2,228 out of 38,262 5%
Number of fully used LUT-FF pairs: 16,334 out of 38,262 42%
Number of slice register sites lost
to control set restrictions: 0 out of 126,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 173 out of 210 82%
Number of LOCed IOBs: 173 out of 173 100%
IOB Flip Flops: 104
IOB Master Pads: 3
IOB Slave Pads: 3
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 120 out of 135 88%
Number using RAMB36E1 only: 120
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 3 out of 270 1%
Number using RAMB18E1 only: 3
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number used as BUFGs: 7
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 16 out of 300 5%
Number used as IDELAYE2s: 16
Number used as IDELAYE2_FINEDELAYs: 0
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 30 out of 300 10%
Number used as ILOGICE2s: 14
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 16
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 118 out of 300 39%
Number used as OLOGICE2s: 76
Number used as OLOGICE3s: 0
Number used as OSERDESE2s: 42
Number of PHASER_IN/PHASER_IN_PHYs: 2 out of 24 8%
Number used as PHASER_INs: 0
Number used as PHASER_IN_PHYs: 2
Number of LOCed PHASER_IN_PHYs: 2 out of 2 100%
Number of PHASER_OUT/PHASER_OUT_PHYs: 4 out of 24 16%
Number used as PHASER_OUTs: 0
Number used as PHASER_OUT_PHYs: 4
Number of LOCed PHASER_OUT_PHYs: 4 out of 4 100%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 14 out of 240 5%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 1 out of 6 16%
Number of IN_FIFOs: 2 out of 24 8%
Number of LOCed IN_FIFOs: 2 out of 2 100%
Number of MMCME2_ADVs: 2 out of 6 33%
Number of LOCed MMCME2_ADVs: 1 out of 2 50%
Number of OUT_FIFOs: 4 out of 24 16%
Number of LOCed OUT_FIFOs: 4 out of 4 100%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 1 out of 6 16%
Number of LOCed PHASER_REFs: 1 out of 1 100%
Number of PHY_CONTROLs: 1 out of 6 16%
Number of LOCed PHY_CONTROLs: 1 out of 1 100%
Number of PLLE2_ADVs: 1 out of 6 16%
Number of LOCed PLLE2_ADVs: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 1 out of 1 100%```
