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Chip Select(s) and power-lines.

  • 1) What happens when both the /CS (for Sid 1) (pin 8 of the IC-socket) and the /I/O-wire (for Sid2) (red wire) are active? ?(


    I know, when these wires are connected in the correct way in the Cbm64 (or Cbm128) (just as the installation-manual says), the Cbm shall never make both wires active at the same time.
    But I'm talking here about using the FpgaSid in a self designed device.



    2) The extra powerline Vdd (pijn 28 ), is that used by the FpgaSid? - I mean the 12V (for a 6581) (or the 9V for a 8580) power-line.


    3) The both Filter-caps (pin 1-2 and pin 3-4), are those used by the FpgaSid?



    A little background story ...


    I'am building a machine with 4 Sid's (2* 6581 and 2* 8580). The Sid's are controlled by an Arduino, simulating a 65xx-data/address-bus. The Sids are selected thru a 74hct138 Decoder.
    Last year, when designing the output amps, my both 6581 Sids got defect by an unknown reason, but probably due to much heat.
    So with the FpgaSid I see a good alternative for the original Sids. And now I though of using the /CS (pin 8 ) for selecting Sid1 and the /IO red-wire for selecting Sid2 in eacht FpgaSid.


    The whole decoding-part is already build and I'm not planning to change that design - unless it is absolutely necessary.
    To my Sid-board are wires for the Data/ Address and control-bus, PLUS 8 seperated /CS-lines (the 74hct138 is a decoder with 8 outputs).


    BUT I have to redesign my Sid-board, so that's why I ask the questions about the powerlines and caps (that can save some space on the board).

  • 1) What happens when both the /CS (for Sid 1) (pin 8 of the IC-socket) and the /I/O-wire (for Sid2) (red wire) are active?

    should be avoided - could work, but it is not tested.


    Since both SIDs share the same address and data lines this is not really a valid mode of operation. The idea behind FPGASID is that whenever both SIDs shall run in parallel FPGASID should be switched to mono mode internally. In Stereo mode both SIDs can be used separately but not both together in the same CPU cycle.


    I think when you are using a 74LS138 for decoding it is assured that only one chipselect is active at a time (one-hot encoding). So that should be fine.


    Don't forget that FPGASID does not listen to the DE00 chipselct in standard configuration. It should be configured in A C64 to use the DE00 address range and then the configuration should be stored to flash permanently.


    2) The extra powerline Vdd (pijn 28 ), is that used by the FpgaSid? - I mean the 12V (for a 6581) (or the 9V for a 8580) power-line.

    Yes, it is used for the Audio output amplifier. If possible connect it to 12V. 9V is OK as well.


    3) The both Filter-caps (pin 1-2 and pin 3-4), are those used by the FpgaSid?

    No.


    I am curious how you project turns out in the end. Please report back here :-)

  • should be avoided - could work, but it is not tested. {to make active both /CS and /IO}

    I asked this one, because I was puzzling how the internal decoding in the FpgaSid is working, when (theoretical) building it with logical gates.


    I understand the programming of the extra registers, which must be easily be done in my project by itself. It support a full space of 8*32-bytes and can each be addressed individual.


    Why not in a Cbm64? Bc mine broke over 25 years ago (black screen when turning on - and I never toke the time to investigate that). At least my disk-drive is still working. :)



    No. {caps needed}

    At least that will save some space, as well on the board, as in height where no FpgaSid-board can be physiscally.
    Ecspecially the (recommended) caps for the 8580 are very big.



    I am curious how you project turns out in the end. Please report back here

    I will sure do.
    The progress can be followed at (the dutch site): http://arsid.ikkie.org/


    (old) Sid-board: http://arsid.ikkie.org/arduikel.php?artikel=sids
    Decoding-board: http://arsid.ikkie.org/arduikel.php?artikel=decoder

  • As for the moment, I designed the next decoding for my ArSid on the Sid-board.


    FpgaSids_v0a.JPG -> (sorry for the dutch texts :D )


    Because all decoding in my project is done by a single 74(hct)138, planned to control (max) 8 seperated Sid's, I have to use this decoding design.
    It's on a seperate board and it won't be easy to rerout the wire arround this IC.


    So extra decoding must be done on the Sid-board. By using FpgaSids, in stead of Sid's, that leave some room for an extra IC.


    In the new design, I still have the seperate Chip Enable (or Chip-select) signals, so to combine these for one FpgaSid, I use a 74hct08.
    This normaly AND-gate is there-for used as an NOR-gate, with inverted inputs. So Enable0, or Enable1 will select FpgaSid0


    To select the Sid1 or the Sid2 in one FpgaSid, I will use an extra Address-line A5, just as is supposed in the original design of the FpgaSid.
    More choises are not usefull in my design, so I will connect the other select lines "A8" (Black-wire) and "I/O1" (Red-wire) at the Gnd/ Vcc - just to not accidently select the Sid2.