letzter Beitrag von Chris-dk am
VC 20 startet mit ganz normalen Startbildschirm,Das SD Interface funktioniert, es lassen sich Programme und Verzeichnisse laden.
Wenn man versucht eine Firmware zu flashen, kommt die im Bild genannte Fehlermeldung.
Habe alle Lötstellen nachgelötet/ausgebessert auch den 74LS245N habe ich getauscht, leider kein Erfolg.
IC´s und alle anderen Bauteile sind richtig eingelötet, auch die DIP sind korrekt (1off,2off,3on,4on)
Kann mir wer einen Tipp geben was kaputt ist?
VC 20 startet mit ganz normalen Startbildschirm,Das SD Interface funktioniert, es lassen sich Programme und Verzeichnisse laden.
Wenn man versucht eine Firmware zu flashen, kommt die im Bild genannte Fehlermeldung.
Habe alle Lötstellen nachgelötet/ausgebessert auch den 74LS245N habe ich getauscht, leider kein Erfolg.
IC´s und alle anderen Bauteile sind richtig eingelötet, auch die DIP sind korrekt (1off,2off,3on,4on)
Kann mir wer einen Tipp geben was kaputt ist?
I have the exact same issue, just finished my FE, and I also get normal startup screeen NO extra ram. Running fediag gives me an 'Error #2' HP=5592, FEflash gives me same error as seen in first post. SD2IEC works fine, I guess it just takes power from the port. The FE came with pre soldered 3.3V regulator and SD card reader, so it was fairly easy to solder the rest. My other RAM expansion works.
Ist das ein Bausatz von Donald?
Ist der CPLD programmiert?
Ich weiss im Moment nicht was Error #2 bedeutet, aber Fe3Diag benötigt keinerlei Firmware, deshalb gibt es nur zwei Möglichkeiten:
Ist das ein Bausatz von Donald?
Ist der CPLD programmiert?
Ich weiss im Moment nicht was Error #2 bedeutet, aber Fe3Diag benötigt keinerlei Firmware, deshalb gibt es nur zwei Möglichkeiten:
- Der CPLD ist nicht oder falsch programmiert
- Die Hardware ist defekt
yeps it is from Retro Donald, all chips are supposed to be programmed. Is there a way to check if the CPLD is running?.
In welcher Speicherkonfiguration wurde das fe3flash.prg gestartet?
Es sollte immer die Grundversion (3,5k) sein.
Gruß Dirk
Ja, in der Grundversion. Es sollte auch lt. Donald bereits eine Firmware vorinstalliert sein. Ich habe dem Sinchai Shop auch schon eine Mail geschrieben.
Die Hardware wurde lt. Anleitung ordnungsgemäß aufgebaut.
Danke für eure Hinweise ! 
In welcher Speicherkonfiguration wurde das fe3flash.prg gestartet?
Es sollte immer die Grundversion (3,5k) sein.
Gruß Dirk
The only settings I can do is the DIP switches on the side?, but I understand that this is not controlling the memory config. I have 3,5K when I start the VIC20 with the FE inserted, so I do not see any extra memory.
My other ram expansion (Per Olofsson's design) works fine.
I have also notified Retro Donald about the issue..
Hast du mal versucht das RAM manuell zu aktivieren? Per POKE Befehl?
Wenn das RAM Banking funktioniert, dann könnte es auch ein Problem des Flash sein.
Hier gibt es einen Thread wo ein anderer FLASH Baustein verwendet wurde. Da funktioniert der Algorythmus etwas anders und deswegen braucht es eine spezielle FE3FLASH Version.
Diese "Vendor ??" Fehlermeldung deutet genau darauf hin, dass es ein anderer Typ von Flash Baustein ist.
Hallo !
Poke 39938,160 oder? er schreibt dann Ready. Wie kann ich feststellen das es auch funktioniert?
LG
Hallo !
Poke 39938,160 oder? er schreibt dann Ready. Wie kann ich feststellen das es auch funktioniert?
LG
No matter what I put into 39938 or 39939 I allways get 156 when i use the Peek command, and always the 3,5K when using the 'print fre(1)'
No matter what I put into 39938 or 39939 I allways get 156 when i use the Peek command, and always the 3,5K when using the 'print fre(1)'
with me as well. I suspect it is the CPLD broken. I have already spoken with Donald. Regards
But I've also been to VC 20 in suspicion. Do you also have the version with the 2 pin power connector?
But I've also been to VC 20 in suspicion. Do you also have the version with the 2 pin power connector?
Mine is the 'new' VIC20 that uses the C64 PSU, it seems as we have the same problem, and also we got a Final Expansion from the new batch that Donald just made, so hopefully we can get it solved :-). I know that Donald is having some problem with his health, so I do not expect him to be available 100%,- hopefully he would have time to help us, and the Forum64 can help pinpoint the problem.
//Chr.
The CPLD is re programmable.
Normaly this part is very strong, I never had a damaged CPLD.
After a POKE for changing the memeory configuration you can simply make a soft reset to see the available memory (or using FRE() )
Alles anzeigenThe CPLD is re programmable.
Normaly this part is very strong, I never had a damaged CPLD.
After a POKE for changing the memeory configuration you can simply make a soft reset to see the available memory (or using FRE() )
Sure, I've done this but the memory is allways the 3.5K, I tried a number of poke combinations (with reset) just to see if I could activate the memory.
The two reset buttons works, the first one 'just' resets the Vic' the other (that is supposed to reset and start the FE), also resets the sd2iec but drops into the normal VIC 20 startup.
I do not have a JTAG interface in my little workshop. I did a re-solder of the board aswell, no effect. The 3.3V is allready done on the PCB at JP1.
The same with my Final Expansion. I ordered a new by Donald, is supposed to be a Christmas present, I'm curious how the new acts.
The two reset buttons works, the first one 'just' resets the Vic' the other (that is supposed to reset and start the FE), also resets the sd2iec but drops into the normal VIC 20 startup.
Yes, one reset button resets all, VIC and also the CPLD of the FE3. This makes sense, so you don't need to power off/on.
The other Reset only resets the VIC. The CPLD registers are unchanged. This makes sense if a game starts with a reset or you want a restart with a specific memory configuration (like a normal memory expansion).
Sure, I've done this but the memory is allways the 3.5K, I tried a number of poke combinations (with reset) just to see if I could activate the memory.
So this could be either if CPLD is not working or if SRAM is not working.
The CPLD has register to configure the memory configuration. This register is writeable and readable. When you test to change memory configuration to activate the memory, please make a PEEK after a POKE command. If the value of a PEEK is same value as the POKE had, the register is working fine.
Please excuse my bad english, I hope you can understand what I say? Please make a POKE to a register with value (value1) and after this a PEEK. Then make a POKE to this register with another value (value2) and another PEEK. The result should be "value1" for the first PEEK and "value2" for the second.
If PEEK always give the same value after a POKE, the register of the CPLD is okay and accessable. So this is a indicator the CPLD ist okay.
I do not have a JTAG interface in my little workshop. I did a re-solder of the board aswell, no effect. The 3.3V is allready done on the PCB at JP1.
To program the CPLD a JTAG is nessecary or a good programmer (for example a GALEP).
I'm sure Donald will do a CPLD test and reprogram for you also.
Alles anzeigen
Yes, one reset button resets all, VIC and also the CPLD of the FE3. This makes sense, so you don't need to power off/on.
The other Reset only resets the VIC. The CPLD registers are unchanged. This makes sense if a game starts with a reset or you want a restart with a specific memory configuration (like a normal memory expansion).
So this could be either if CPLD is not working or if SRAM is not working.
The CPLD has register to configure the memory configuration. This register is writeable and readable. When you test to change memory configuration to activate the memory, please make a PEEK after a POKE command. If the value of a PEEK is same value as the POKE had, the register is working fine.
Please excuse my bad english, I hope you can understand what I say? Please make a POKE to a register with value (value1) and after this a PEEK. Then make a POKE to this register with another value (value2) and another PEEK. The result should be "value1" for the first PEEK and "value2" for the second.
If PEEK always give the same value after a POKE, the register of the CPLD is okay and accessable. So this is a indicator the CPLD ist okay.
To program the CPLD a JTAG is nessecary or a good programmer (for example a GALEP).
I'm sure Donald will do a CPLD test and reprogram for you also.
Your english is fine!, much better than my German. I made a small basic program where I can put in a value in address 39938, and 39939, then the program shows the Peek of each address aswell as print a fre(1) in order to see free ram.. No matter what I put into the two addresses I allways got 156 as output. I did a reset and a print fre (1) to see memory no chance at all... I suspect that the CPLD could be the problem.
Your english is fine!, much better than my German. I made a small basic program where I can put in a value in address 39938, and 39939, then the program shows the Peek of each address aswell as print a fre(1) in order to see free ram.. No matter what I put into the two addresses I allways got 156 as output. I did a reset and a print fre (1) to see memory no chance at all... I suspect that the CPLD could be the problem.
The FRE() function doesn't give a correct value. Cause it only show the difference between BASIC start end BASIC end address, and this both ZP pointer are set from the kernel reset procedure.
But, you say PEEK of register always give 156, independently of any POKE bevore!
So it is clear for me the CPLD register is not accessable.
This means, CPLD is not working.
Either CPLD is damaged or not/invalid programmed.
You took a 3,3V CPLD? My original prototype FE3 uses an Atmel 1504 which is a 5V type. But I'm sure Donald knows why using this CPLD.
Did you ask donald for helping you? Maybe he could send you another CPLD?
Did you ask your friends if there is a suitable JTAG programmer available?
I'm sure we can get it run. 
Alles anzeigenThe FRE() function doesn't give a correct value. Cause it only show the difference between BASIC start end BASIC end address, and this both ZP pointer are set from the kernel reset procedure.
But, you say PEEK of register always give 156, independently of any POKE bevore!
So it is clear for me the CPLD register is not accessable.
This means, CPLD is not working.
Either CPLD is damaged or not/invalid programmed.
You took a 3,3V CPLD? My original prototype FE3 uses an Atmel 1504 which is a 5V type. But I'm sure Donald knows why using this CPLD.
Did you ask donald for helping you? Maybe he could send you another CPLD?
Did you ask your friends if there is a suitable JTAG programmer available?
I'm sure we can get it run.
The AFT1504 is a ATF1504ASV, I've tried to remove the label, and the chips also says 1504ASV so it is a 3.3V 
. Since the poke/peek shows that I cannot change the registers, I belive that the CPLD needs some checking. I have not heard from Donald, but I will email him with this thread on the link.
