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letzter Beitrag von Draco am

Visual 6502

  • Tach,


    das hier ist ziemlich beeindruckend: LINK


    Visualisierung eines 6502.



    Have you ever wondered how the chips inside your computer work? How they process information and run programs? Are you maybe a bit let down by the low resolution of chip photographs on the web or by complex diagrams that reveal very little about how circuits work? Then you've come to the right place!


    The first of our projects is aimed at the classic MOS 6502 processor. (...) In the summer of 2009, working from a single 6502, we exposed the silicon die, photographed its surface at high resolution and also photographed its substrate. Using these two highly detailed aligned photographs, we created vector polygon models of each of the chip's physical components - about 20,000 of them in total for the 6502. These components form circuits in a few simple ways according to how they contact each other, so by intersecting our polygons, we were able to create a complete digital model and transistor-level simulation of the chip.


    This model is very accurate and can run classic 6502 programs, including Atari games. By rendering our polygons with colors corresponding to their 'high' or 'low' logic state, we can show, visually, exactly how the chip operates: how it reads data and instructions from memory, how its registers and internal busses operate, and how toggling a single input pin (the 'clock') on and off drives the entire chip to step through a program and get things done

  • wenn sich jetzt mal wer hinsätzen täte und damit rauskaspert was genau opcode $8b (ANE) macht, das wäre super :) (evtl vorhar mal einen anderen illegalen testen um zu sehen ob die simulation das richtig macht).


    Wer weiß, ob damit die illegalen Opcodes wirklich korrekt simuliert werden...
    Hier der Auszug aus der FAQ (Hervorhebungen von mir):


    Zitat

    * How does the simulation differ from the real chip?


    The simulator is running an idealized "digital" circuit based on our model of the chip's network of transistors and wires. It does not account for "analog" behavior (resistance, capacitance, leakage), has no propagation delays, and transistors switch on and off instantaneously. The real chip uses the same network of transistors (barring any mistakes we may have made in our model), but these transistors are analog devices. Our simulation uses a few simple heuristics to account for the differences in behavior between the actual analog circuits and our idealized digital model. In our simulation, if a transient short occurs from power to ground, ground wins. This may happen in our iterative solver as the simulation state is converging. Also, when two floating regions are switched together, their final voltage is taken from the region with the most components. This is a simple but completely non-physical way to account for capacitance.

  • Sind die Illegalen Opcodes nicht einfach Nebeneffekte von logischen Vereinfachungen?
    Dann sollten sie sich in Simulation und Praxis nicht von den normalen Opcodes unterscheiden. Also kein "analoges Tamtam" oder sowas.