1551 CPU/TIA-Replacement Board (WIP)

Es gibt 49 Antworten in diesem Thema, welches 7.407 mal aufgerufen wurde. Der letzte Beitrag (26. Januar 2024 um 14:54) ist von kinzi.

  • Sorry if I'm very (very, very,.....) absent from the forum........

    I don't find the schematic of the board in object, so I have to immagine,

    looking the chips on the board I'm afraid that a specific behaviour was not be considered:

    when the 6502 read the address $0000/1 two different devices try to drive the DATA bus: the (page zero) RAM and the external PIO:

    this is a classic "bus conflict".

    An easy way to prevent this is feeding the A14 of 6510T socket with the 6502 A14 passed through an "OR" gate with the other gate input feeded with a signal that is "H" when the 6502 address is $0000/1.

    In this manner when the 6502 ask for $0000/1 the 1551 motherboard decode the I/O hole ($400x) where nothing responde that is not on your little board....

  • I don't find the schematic of the board in object, so I have to immagine,

    I haven't released it yet .... that might be the cause ... :smile:

    when the 6502 read the address $0000/1 two different devices try to drive the DATA bus: the (page zero) RAM and the external PIO:

    this is a classic "bus conflict".

    There is no conflict. If the CPU accesses $0000/$0001, the RAM is knocked out, of course.

  • An easy way to prevent this is feeding the A14 of 6510T socket with the 6502 A14 passed through an "OR" gate with the other gate input feeded with a signal that is "H" when the 6502 address is $0000/1.

    In this manner when the 6502 ask for $0000/1 the 1551 motherboard decode the I/O hole ($400x) where nothing responde that is not on your little board....

    That's the way it is done ... although with A13.

    Wieso kann ich plötzlich Beiträge, die ich gerade eben geschrieben habe, nicht mehr ediitieren?

  • Little note:

    during a bus conflict wins the device that drive more heavy the data lines, so it's normal that a C-MOS win vs. traditional RAM and that a N-MOS not....

    Does this sound familiar?

  • Little note:

    during a bus conflict wins the device that drive more heavy the data lines, so it's normal that a C-MOS win vs. traditional RAM and that a N-MOS not....

    Does this sound familiar?

    Please note: There is no conflict.

  • Little note:

    during a bus conflict wins the device that drive more heavy the data lines, so it's normal that a C-MOS win vs. traditional RAM and that a N-MOS not....

    Does this sound familiar?

    Please note: There is no conflict.

    Sorry, I wrote the second post before reading yours....

    OK, when the schematic will be released we can see it, we have only to wait.

    Also the MOS6510T replacement has a similar potential problem, I think that also in that project the conflict on $0000/1 address is resolved for a wellworking

  • Also the MOS6510T replacement has a similar potential problem, I think that also in that project the conflict on $0000/1 address is resolved for a wellworking

    I don't know what you are referencing ... I didn't design a 6510T only replacement.