D0..D7 is the C64\C128 data bus.
D0io..D7io is the bidirectional data bus inside the 8726 related to D0..7.
D0..7 drivers\buffers have identical chip layout, so we just focus on D0.
On the input side, D0 is sampled with a transparent latch during PHI2.
The output of the latch is placed on the D0io bus by a non_inverting buffer
controlled by OE_DI# (low active), which is generated in "3) CS#".
On the output side, we have a non_inverting driver fed by D0io, driving D0,
controlled by OE_D (high active), which is generated in "3) CS#".
Drivers have output FETs switching non_overlapping to GND\VCC
it's a variation of the driver we already had in "5) rw",
making creative use of a RS flipflop built from two NOR gates.