Hello all,
I'm working on collecting detailed test vectors from a few MOS6526's I have lying around here, using an Arduino as a stimulator for the pins. What I want to do is create an as good as possible Verilog and C model from that which may be further refined based on other information like schematics. For that a good reference of cycle-by-cycle pin states is very useful.
I'd like to hear from any of you if you have some other links or details to share, about existing test vectors or of the internal working of the CIAs. I've put details I've collected so far down below.
The tests I do are cycle-by-cycle stimulation and observation of the IC after each cycle. There is a readReg(address, cycle) and a writeReg(address,data) function that do most of the work. With the cycle param you can chose to cyclle phi2 low once or keep it high.
A very nice trick this IC allows is that when you keep PHI2 high, you can read the internal registers combinatorially without advancing any state machines internally (at least so far that seems the case). So with some simple arduino code and some pin toggling you can get a lot of insight to the visible registers after each cycle.
So far, I'm quite happy with my progress. But I am now getting to a phase where I'd like to ask if anyone knows of any existing test vector sets, at a lower level than the C64 assembler level tests I've seen in VICE.
References and details I have been able to find myself so far:
- VICE has a C model, but it seems a bit too emulator centric to exactly follow for me.
- In this forum AndroSID has posted several die shots, but I'm not really sure how to continue from those.
- I've found 2 different synthesizable models: from the MIST project and from the c65gs project
https://github.com/mist-devel/c64/blob/master/rtl/mos6526.v
https://github.com/gardners/c65gs/blob/master/cia6526.vhdl
The vhdl model seems to have some nice additions, but the synthesized size is around twice as large as I'd expect. I've not checked the MIST model in detail for synthesis.
My own measurements at cycle level seem to suggest some differences at least with both models.
I've also built my own verilog model, which has some differences with both models, but that isn't salonfahig yet. I've been able to use Xilinx ISE 10.1 to synthesize to a 5V tolerant part, the old Spartan II XC2S30 - it needs around 280 flipflops. I've also made the Alarm and TOD latch registers optional for synthesis but this doesn't help enough to get it into a smaller part.
Some low-level bugs/features I've noticed in my tests, not sure how much of this is well-known:
// Conclusions so far:
// Output mux from internal latches is just combinatorial, PHI2=1, CSN=0, RWN=1.
// PA/PB inputs are latched on posedge of PHI2 and can then be read at negedge. Observable as a 1/2 cycle input delay.
// PA/PBout are latches and can be written multiple times during 1 phi2=1. However outputs only change on next PHI2 negedge. So the PAout, PBout are 2 latches, you read the first latch back, the 2nd latch goes to the output.
// IRQ bit 7 of ICR is one cycle later set also one cycle later cleared than a timer irq is set.
// Reading ICR seems to reset the ICR the next cycle.
// Writing ICR seems to also clear the ICR, 2 cycles later, in my 6526R4. (without any read)
// IRQN output pin changes 0->1 and 1->0 on the negedge of phi2. IRQN output is made inactive immediately when reading ICR.
// When TA generates an IRQ every cycle (TAL=TAH=0, start=1), a read from ICR will set IRQN high (inactive) for one cycle. But bit 7 of ICR stays high (active).
// Test mode: A on phi2, B one-shot on A. When A reaches underflow:
// tal: 01 05 05 04 //
// tbl: 00 00 02 02 // one-shot reloads, clears start bit in crb.
// icr: 18 19 9B 9B // B irq one cycle later than A.
// crb: 49 49 48 48 // start bit is cleared
// Bit 0 of CRA/CRB is cleared when in one-shot mode on the
// Timers reload view must be due to reading back a latch halfway through processing.
// latch-based counter: Cant be built. So 2 latches are used with a minus inbetween. What is read is the phi2=1 latch, timer out is then phi2=0 active
// phi2=0
// phi2=1 latch muxes ta_l, underflow
// Toggle on PB and CNT in has no immediate same-cycle effect, PB unchanged and TAL unchanged. Both are re-synced.
// Toggle on PB5 during PHI2=1, has no effect on next PB scan.
// Toggle on PB5 during PHI2=0, before scan with PHI2=1, has direct effect.