MOS6526 CIA detailed test vectors and models

Es gibt 44 Antworten in diesem Thema, welches 13.068 mal aufgerufen wurde. Der letzte Beitrag (12. Januar 2021 um 00:20) ist von merlintwa.

  • So, I conclude from your FPGA experiments, you've seen max transfer rates close to 2 phi2 clocks per bit using a 6526R4 in a C64 as input, when you first phase-align the external FPGA with the chip. You then also make CNT only high for half of a PHI2 cycle, followed by 1.5 cycles low. Is that correct?

    No, a short CNT low phase followed by a 1,5 PHI2 cycle high phase.

    This is what the "best case" would look like for a transmission of a "0" bit followed by a "1" bit:

    Code
                 |<- 2 phi2 cycles ->|
    
    PHI2 ‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾
    
    CNT  ‾‾‾‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_
    SP   ‾‾‾‾‾‾‾‾|___________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_
    
                     ^              ^ 
                     1              2

    From what I (think to...) understand, the 6526 would register the positive CNT edge at the negative PHI2 edge at "1" and sample SP 1,5 cycles later at the second positive PHI2 edge at "2". The whole CNT/SP transfer cycle is 2 PHI2 cycles. You could even go slightly faster for one bit by making the CNT "low" phase shorter, but that doesn't gain you anything, because if the time for 1 bit isn't a multiple of a PHI2 cycle, you lose the optimal phase offset for the next bit(s).

    And this is the "worst case":

    Code
                 |<-    ~3 phi2 cycles     ->|
    
    PHI2 |____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾
    
    CNT  ‾‾‾‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__|‾‾‾‾‾‾‾‾‾‾
    SP   ‾‾‾‾‾‾‾‾|___________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾
    
                             ^              ^ 
                             1              2

    As the negative PHI2 edge just misses the positive CNT edge, SP is sampled ~1 PHI2 cycle later than in the "best case". So in order to work with all possible phase offsets, you have to make SP valid for one more PHI2 cycle.

    I actually don't know much about chip design, that's why I can't really follow all your explanations. I merely took a black box approach and checked what signals lead to which bits being sampled in the SR. I can't really comment on what the actual design would have to look like to lead to this behaviour.

    Regarding the IRQ issue: I only brought it up because I thought that you said you found that the SR IRQ has a similar issue as the "timer b bug". As that apparently was a misunderstanding, I wouldn't read too much into that. I didn't do enough research to be confident that the IRQ really wasn't set for the SR. In the end it could well be something as simple as a bad connection on the IRQ probe.

  • Thank you for the very clear pictures!

    I have been progressing this week trying to further integrate your findings looking for the issue in my tests.

    I have added all possible CNT pulse lengths and phase offsets I could think of, plus some more-or-less random stimulus to see what the logic of CNT is.


    After that work I found I can now reproduce anything the CIA reports back on the Timer A output when in CNT count mode, using this input circuit: CNT is an input to a normal D-type Flip-Flop with an Asynchronous reset input. This feeds another flipflop that synchronizes the detected posedge to the PHi2 clock domain, and its output also resets the edge detector. So during the actual internal count pulse (when cnt_rr=1), you can do whatever you want on the CNT input - it is ignored.

    The funny thing is, the duty cycle issue you mention doesn't seem to come up in my tests for timer A. The rising edge is detected regardless if it is just a very short 1->0->1 pulse (like in your graph) or if it is a very short 0->1->0 pulse, or of it already goes 1->0 in the cycle before the posedge. Maybe it is a Serial Register exclusive issue, to do with that trasparent path I found. I will research that.

    The actual implementation of the CNT input stage might not be this exact circuit but this is the closest I can come up with explaining everything I've tested. Timer A then decreases itself using cnt_rr (which takes one cycle). Then if you read the TAL register the cycle after that, it is decreased.

    always @(negedge phi2 or resn) begin

    if(~resn) cnt_rr<= Bitte melde dich an, um diesen Link zu sehen. 0;

    else cnt_rr<=Bitte melde dich an, um diesen Link zu sehen. cnt_r;

    end

    always @(posedge cnt or posedge cnt_rr) begin

    if(cnt_rr) cnt_r<=Bitte melde dich an, um diesen Link zu sehen. 0;

    else cnt_r<= Bitte melde dich an, um diesen Link zu sehen. 1;

    end

    I am assuming the CNT input stage is also used for clocking in SDR.

    I will check if the FLAGN input has the same sort of behavior as this.

  • Anyway, when you are ready, and if you are willing, we would love to incorporate your work into the MEGA65 and give a good testing out there. We would need to re-integrate our extra 16 state exposure registers to support freezing, but that's not hard.

    In short: We really love and admire what you are achieving :)

    LG

    Paul.

  • After that work I found I can now reproduce anything the CIA reports back on the Timer A output when in CNT count mode, using this input circuit: CNT is an input to a normal D-type Flip-Flop with an Asynchronous reset input. This feeds another flipflop that synchronizes the detected posedge to the PHi2 clock domain, and its output also resets the edge detector. So during the actual internal count pulse (when cnt_rr=1), you can do whatever you want on the CNT input - it is ignored.

    The Verilog you posted suggests that the second flip flop is clocked from the negative PHI2 edge, which matches exactly what I observed, doesn't it? The time between the positive CNT edge and the times that I marked "1" is the period between the two events. The difference between the Timer A logic you describe and the SR logic would be that the latter takes one PHI2 cycle longer.

    The funny thing is, the duty cycle issue you mention doesn't seem to come up in my tests for timer A. The rising edge is detected regardless if it is just a very short 1->0->1 pulse (like in your graph) or if it is a very short 0->1->0 pulse, or of it already goes 1->0 in the cycle before the posedge. Maybe it is a Serial Register exclusive issue, to do with that trasparent path I found. I will research that.

    I think that's a misunderstanding. You're probably referring to what I wrote in Bitte melde dich an, um diesen Link zu sehen.? Maybe "duty cycle" was bad wording. I was talking about the behaviour of the 6526 when sending. It sets CNT low at the beginning of a bit cycle and then does one low -> high transition at 50% of the bit cycle and keeps CNT high for the rest of the bit cycle. What I meant is that this transition has to be earlier than the 50% mark of the bit cycle because in the worst case it can take ~2,5 PHI2 cycles from the positive edge of CNT until SP is sampled (as outlined in Bitte melde dich an, um diesen Link zu sehen.) while 50% of the bit cycle is only 2,0x PHI2 at the highest data rate.

    That does *not* mean, that something like this, with only a short positive CNT pulse, would not work:

    Code
                    |<-  >2 phi2 cycles    ->|
    PHI2 |____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾|____|‾‾‾‾
    CNT  ‾‾‾‾‾‾‾‾|__|‾‾|_____________________|‾‾‾‾‾‾‾‾‾‾‾‾‾
    SP   ‾‾‾‾‾‾‾‾|___________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾
                             ^              ^ 
                             1              2

    Is that what you meant? I never checked anything like that, I only experimented with having the CNT low -> high transition at different points in the bit cycle.

    What I don't understand is the "... or of it already goes 1->0 in the cycle before the posedge" part. I guess "1->0" refers to CNT (?), but "posedge" of what? PHI2? Shouldn't this be "negedge" then? In that case I would agree (it's what my "diagram" above shows, right?).

  • Hi thierer,

    Yes your observations and mine agree, I used your descriptions as an input to move ahead and do all the many pulse shape variations in my testbench. Then from those pretty strange results try to come up with the verilog above, and run that against the testbench.

    Now from the measurements I have, the "best case" you describe does work, but not reliably. The unreliability is because the last bit (LSB) of every byte is sampled from the *next* byte, with a transparent path through the IC. This may or may not cause issues by itself.

    But what is more problematic is if there is a mix of 2-phi2 and 3-phi2 cycle bits.

    In the graph below (same as earlier but cleaned up a bit) the IC is first stimulated with 3-phi2 cycles per bit 0x1D. Then the stream switches to 2-phi2-cycle sending 0xE7. If you look closely, you can see one bit has been lost between the move from 3 to 2 phi2-cycle. The last bit of the 2nd byte is already shifted out before the SR register is loaded from the 8-bit-shift register internally, the output goes to 0xCF (which is 0xE7 shifted by one bit and the LSB from the next byte).

    So in this case where there are occasional 2-phi2 cycle bit in a stream, you will lose bits occasionally. This shorter 2-phi2 could also be influenced by a little setup and/or hold time and a little clock jitter (causing an instantaneous phi2 period to be a fraction shorter than average), so might be anything shorter than 2.1 phi2-cycles in a stream. Losing bits will probably lead to the internal bit shift counters of both systems getting out of sync. And that will cause a hang.

    The graph shows SP pin 0001 1101 1110 0111.