Ich weiß zwar noch nicht so 100%, um was es da jeweils geht 
, aber mir sind letztens drei Projekte fürs Nexys-Board über den Weg gelaufen und will sie "der Vollständigkeit halber" hier mal erwähnen.
Vielleicht hat ja der eine oder andere mal Lust, da reinzuschnuppern ...
Das wäre als Erstes dieses Projekt:
QuoteWe are pleased to release MIPSfpga Labs 2.0 (released July 3rd 2017). Please note that the last release was designated MIPSfpga Fundamentals v1.3.
MIPSfpga 2.0 includes a series of laboratories to acquaint you with the MIPSfpga (microAptiv) core, its memory system, and system-on-chip (SoC) design using MIPSfpga platform on the Nexys A7 (Formerly Nexys4 DDR) FPGA board.
Als Zweites dieses:
QuoteThe Raisin64, like most computer processors, is a collection of various processing elements and memories, creating what is presently a pipelined 64-bit Harvard RISC architecture. While the initial semester of work focused on getting the design off the ground: designing the instruction set, laying out the execution pipeline, preparing the tools, etc., the eventual goal is to create a CPU capable of running a modern general purpose operating system. This also includes porting all the required debug utilities, assembler, compiler, and other tools necessary to accomplish that goal.
Nexys 4 DDR Reference Implementation
The Nexys 4 DDR (Using a Xilinx Artix-7 series XC7A100T-1CSG324C) was chosen as the reference implementation due to its copious hardware resources, interactive IO, and sufficient memory for a general purpose operating system using the onboard resources. The Raisin64 was connected to memory-mapped peripherals providing access to the LEDs, Switches, and a custom written character oriented VGA controller.
The example project is accessible at https://github.com/ChrisPVille/raisin64-nexys4ddr
Und als Drittes dann:
QuoteDisplay MoreAbout lowRISC
lowRISC is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year.
Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board.
lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community.
The build environment and pre-built images (if legally allowed to be distributed) support a competitively priced Nexys™4 DDR Artix-7 FPGA Board with 128M RAM, as well as the Genesys2 Kintex-7 FPGA Board with 1GB RAM.
